The present invention relates to electronic systems, devices and methods of operation thereof, and more particularly, to electronic systems and devices having components with current demands that are highly correlated with a common clock signal or other timing reference, and methods of operation thereof.
Communications systems are increasingly making use of highly-integrated devices for implementing functions such as network hubs, switches, routers, repeaters and the like. For example, integrated communications circuits such as fast Ethernet transceivers (FETs) have been developed that can provide multi-port media access control for physical media such as twisted pair cable, fiber optic lines and the like. Typical multi-port transceivers or media access control devices (MACs) employ multiple copies of single port transceiver circuits that share common circuit blocks such as clock generators and reference voltage and current generators. Clock signals used to control the driving of physical media by transceivers on such a chip are commonly driven from a common point on the chip, or are phase-locked to a clock signal generated by a master clock generation circuit.
Transceivers on conventional multi-port communications devices typically drive physical media at multiple ports in phase. For example, in a conventional multi-port device configured as a repeater, data received at an input port is transported to a plurality of output ports and then typically is applied to physical media at the ports in a simultaneous or nearly simultaneous fashion. This can give rise to a significant instantaneous current demand when the output channels are driven. Devices that supply current to the output transceivers, including on-chip regulators and off-chip power supplies, generally must be sized to meet this instantaneous demand. In addition, current spikes associated with increased instantaneous demand can cause noise that can compromise system performance. Although these performance issues are acute in communications devices, similar power and noise management issues may arise in other electronic devices and systems, e.g., synchronous systems such as computers, microprocessors, digital signal processors, and the like, that include components having current demands that are highly-correlated with a shared clock domain.
It is has been proposed that noise problems associated with the simultaneous current demand of circuits can be ameliorated by staggering the control signals that operate the circuits, as described, for example, in xe2x80x9cNoise Reduction in VLSI Chips,xe2x80x9d IBM Technical Disclosure Bulletin, vol. 33, no. 9, pp. 476-477 (February 1991), xe2x80x9cStaggered Block Write in a Storage Array,xe2x80x9d IBM Technical Disclosure Bulletin, vol. 30, no. 10, p. 298 (March 1988), xe2x80x9cElectromagnetic Interference Reduction Through Time Distribution of Clock Signals,xe2x80x9d IBM Technical Disclosure Bulletin, vol. 37, no. 7, pp. 165-168 (July 1994), xe2x80x9cSelf-Adjusting Stagger Circuit for Drivers,xe2x80x9d IBM Technical Disclosure Bulletin, vol. 28, no. 5, pp 2178-2180 (October 1985), xe2x80x9cOutput Buffer Control Logic,xe2x80x9d IBM Technical Disclosure Bulletin, vol. 34, no. 8, pp. 300-303 (January 1992), and U.S. Pat. No. 5,646,543 to Rainal. These conventional approaches typically utilize chains of delay elements, e.g., chains of inverters or logic gates, to provide the staggered control signals.
However, devices such as high-speed network transceivers typically operate under demanding timing requirements. For example, a multi-port fast Ethernet transceiver (FET) chip implementing a 100Tx (IEEE standard 802.3) class 1 or a class 2 repeater has a through-time requirement of 0.7 microseconds and 0.46 microseconds, respectively, i.e., times on the order of the period of a typical 20-25 MHZ clock used to operate the chip. In order to implement control signal staggering for the multiple transceivers in such a chip, precise and stable delays on the order of nanoseconds are desirable to avoid errors caused, for example, by violation of set-up and hold time requirements of the transceivers. Conventional delay chains may be incapable of providing sufficiently precise and stable delays.
In light of the foregoing, it is an object of the present invention to provide electronic systems and devices that exhibit reduced instantaneous switching current demands in comparison to conventional devices.
It is another object to provide systems, devices and operating methods that can provide improved noise suppression.
It is another object of the present invention to provide systems, devices and operating methods that can implement control signal staggering with precise and stable phase control.
These and other objects, features and advantages are provided according to the present invention by apparatus, devices and methods in which a first phase control circuit, e.g., a phase locked loop, is operative to synchronize an output signal thereof through intermediate generation of a phase control signal, and in which a plurality of second phase control circuits, e.g., delay elements, is operative to produced phased output control signals from at least one input control signal responsive to the phase control signal. For example, in an embodiment of the present invention, a phase locked loop circuit includes a ring oscillator controlled by a loop control circuit that generates the phase control signal from a reference clock signal and an output of the ring oscillator. The phase control signal generated by the phase-lock loop circuit is applied to a string of delay circuits that produce a plurality of phased output control signals that are used to drive a plurality of transmitters, thus providing an apparatus for time-distributing current demand by the transmitters.
The present invention arises from a realization that precise and stable phased control of current demand by components such as transmitters can be achieved by phase-locking an oscillator circuit comprising a sequence of delay circuits to a reference clock signal to determine a phase control signal that can be used to produce precise and stable delays in similar or identical delay circuits. These delay circuits can be used to generate precisely phased control signals for operating the components, without recourse to other methods of defining precise small time intervals, such as the generation of extremely high-frequency clock signals.
In particular, according to the present invention, in an electronic system including a plurality of components, each of which are operative to demand current responsive to a control signal applied thereto, an apparatus for time-distributing current demand comprises a first phase control circuit configured to receive a reference clock signal and operative to generate a synchronized output signal therefrom, the first phase control circuit generating a phase control signal for synchronizing the output signal to the reference clock signal. A plurality of second phase control circuits is responsive to at least one input control signal and to the phase control signal and operative to apply a plurality of phased output control signals to the plurality of components, the phased output control signals phased with respect to one another by time intervals that are dependent upon the phase control signal. The first phase control circuit may comprise a phase-locked loop circuit operative to produce the phase control signal from a comparison of the reference clock signal and the output signal, and the plurality of second phase control circuits may comprise a plurality of delay circuits, each configured to receive the phase control signal and an input control signal and operative to produce a delayed output signal that is delayed with respect to the input control signal by a time interval dependent on the phase control signal.
In an embodiment according to the present invention, the first phase control circuit comprises a ring oscillator including a first string of delay circuits operative to produce a plurality of output signals that are phased with respect to one another according to a phase control signal applied thereto. A loop control circuit is configured to receive a reference clock signal and an output signal from a delay circuit of the ring oscillator and operative to produce the phase control signal therefrom. The plurality of second phase control circuits may comprise a second string of delay circuits, e.g., delay circuits such as those in the first string.
In another embodiment according to the present invention, a communications device, e.g., an integrated circuit device such as a fast Ethernet transceiver (FET), includes a plurality of transmitters, each of which is operative to drive a physical medium responsive to a control signal applied thereto. A first phase control circuit, e.g., a phase-locked loop circuit, is configured to receive a reference clock signal and operative to generate a synchronized output signal therefrom, the first phase control circuit generating a phase control signal for synchronizing the output signal to the reference clock signal. A plurality of second phase control circuits is responsive to at least one input control signal and to the phase control signal and operative to apply a plurality of phased output control signals to the plurality of transmitters, the phased output control signals phased with respect to one another by time intervals that are dependent upon the phase control signal. The device may further comprise a register coupled to an input of one of the plurality of transmitters, and the plurality of second phase control circuits may include a phase control circuit coupled to the register and operative to apply a first phased output control signal thereto, and a phase control circuit coupled to the one transmitter and operative to apply a second phased output control signal thereto. In this manner, precise timing compensation may be provided to prevent data loss in configurations such as network repeaters or switching hubs.
Related methods of operating such systems and devices are also described.